數(shù)字邏輯與計算機硬件設計基礎（英文原版）

定　價：￥58.00

作　者：	（美）M.Morris Mano著，（美）Charles R.Kime著
出版社：	電子工業(yè)出版社
叢編項：	國外計算機科學教材系列
標　簽：	邏輯學

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ISBN：	9787505376625	出版時間：	2002-07-01	包裝：	平裝
開本：	24cm	頁數(shù)：	650	字數(shù)：

內(nèi)容簡介

　　本書是計算機科學、計算機工程和電氣工程等專業(yè)的學生學習邏輯電路設計的入門教程。全書共7章和一個附錄，前4章介紹數(shù)制、開關代數(shù)、真值表和卡諾圖，并講解了邏輯函數(shù)的化簡以及組合系統(tǒng)的分析與設計；后3章介紹時序系統(tǒng)的分析與設計、移位寄存器和計數(shù)器、可編程邏輯器件、用列表法和狀態(tài)分割法進行狀態(tài)化簡和狀態(tài)分配；附錄部分介紹了4個實驗操作平臺及25個實驗室作業(yè)。要學好邏輯電路設計這門課程，需要掌握好三個環(huán)節(jié)：理論、習題和實驗。本書緊緊抓住這些教學環(huán)節(jié)，系統(tǒng)地闡述了邏輯設計的核心內(nèi)容，尤其突出了系統(tǒng)的分析和設計方法。對于需要學生通過練習進一步鞏固的重點內(nèi)容，書中均布置了適量作業(yè)。在每章講述內(nèi)容之后專門安排了一節(jié)解題實例和一節(jié)習題。本書是學習邏輯電路設計難得的一本好教材，既可作為計算機、電氣工程和通信、電子等專業(yè)學生的教材或教學參考書，也可供相關專業(yè)工程技術人員參考。譯者序《邏輯電路設計基礎》是計算機、電氣工程及通信、電子等專業(yè)學生的一門重要的技術基礎課。因此，學好本門課程，是對以上各個專業(yè)學生的一個基本要求。為了幫助中國學生學好這門課程，電子工業(yè)出版社引進了《邏輯電路設計基礎》一書。該書緊緊抓住理論、習題和實踐等教學環(huán)節(jié)，理論與實踐并重，是一本很有特色的教材。本書全面系統(tǒng)地闡述了邏輯電路設計的核心內(nèi)容，尤其突出了系統(tǒng)的分析和設計方法。本書的特點體現(xiàn)在如下幾個方面：1．內(nèi)容深入淺出問題的講授總是先從給讀者一個粗略的總體概念開始，譬如第1章即給出了組合邏輯設計的過程，使讀者對邏輯設計有一個初步了解，不致使學生在后面內(nèi)容的學習中對問題感到茫然，然后介紹邏輯設計過程中各個步驟所需的理論、工具和方法，再到整個系統(tǒng)的設計。做到由淺入深，從個別到一般，把內(nèi)容逐步擴展開來，直到把問題講述得十分透徹。2．實用性強這主要體現(xiàn)在三個方面，一是書中有大量的例題、解題實例和習題，使學生便于學習和掌握書中介紹的各種方法和技巧，也便于自學；二是分析和設計所用的電路大多是商用的集成電路芯片，使學生在學習過程中即完成了從原理電路到真實電路的過渡，提高實際應用能力；三是在附錄中介紹了四種實驗平臺，提供許多實驗室作業(yè)，使學生能理論聯(lián)系實際，進一步鞏固所學知識。3．優(yōu)化設計優(yōu)化設計既可降低實現(xiàn)成本，又能減小電路的體積和提高電路的可靠性。這是本書始終貫穿的基本思想，從邏輯函數(shù)的化簡求最優(yōu)解，到組合邏輯電路設計時所用的門數(shù)最少、芯片數(shù)最少、芯片的種類最少、芯片之間的連線最少，再到時序電路設計時通過狀態(tài)化簡和狀態(tài)分配，使所用存儲電路最少、組合邏輯最少等。在求最優(yōu)解的過程中，提煉出一些規(guī)范性的化簡方法，如迭代合意法化簡邏輯函數(shù)、狀態(tài)分割法進行狀態(tài)化簡和狀態(tài)分配等，都體現(xiàn)了這一思想。使學生？諮罷庋幻拋ㄒ禱】蔚氖焙潁躍醯匱梢？個“經(jīng)濟頭腦”，從而在實際設計中，力爭最優(yōu)。4．適于作為大學生的教材本書是作者多年教學工作的總結(jié)，其手稿征求過美國許多大學同行們的意見，并且，前期書稿由作者本人及其同事進行過多個輪次的教學。最后經(jīng)過多所大學的同行審閱，幾經(jīng)修改才正式出版。在書的前言部分作者給出了各部分內(nèi)容的參考學時數(shù)，并根據(jù)不同具體情況對內(nèi)容的取舍，供老師們在教學中參考，因此，本書非常適于作為大學生的教材或教學參考書。本書的前言及第1章由楊匡漢教授翻譯；第2～6章由殷洪璽博士翻譯；第7章和附錄由李正斌博士翻譯。由殷洪璽博士對全書譯稿作了統(tǒng)一校訂，最后由徐安士教授審閱了全書。書中出現(xiàn)的名詞術語，本著“名從主人”的原則，一般都選用國內(nèi)較為通用的譯名。對于一些還沒有通用譯名的術語，譯者本著“一名之立，旬月躊躇”的精神，反復推敲，才把譯名定下來。例如第3章提到的“迭代合意法”（IteratedConsensus）和第5章談到的“時序徑跡”（TimingTrace）等。由于譯者水平有限，加之時間匆促，譯文中的不妥之處，希望廣大讀者給予批評指正。

作者簡介

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圖書目錄

Chapter 1 3
DIGlTAL COMPUTERS AND INFORMATION
1-1 Digital Computers
Information Representation
Computer Structure
More on the Generic Computer
1-2 Number Systems
Binary Numbers
Octal and Hexadecimal Numbers
Number Ranges
1-3 Arithmetic Operations
Conversion from Decimal to Other Bases
1-4 Decimal Codes
BCD Addition
1-5 Alphanumeric Codes
ASCII Character Code
Parity Bit
1-6 Chapter Sununary
References
Problems
CHAPTER 2 27
COMBINATIONAL LOGIC CIRCUITS
2-1 Binary Logic and Gates
Binary Logic
Logic Gates
2-2 Boolean Algebra
Basic Identities of Boolean Algebra
Algebraic Manipulation
Complement of a Function
2-3 Standard Forms
Minterms and Maxterms
Sum of Products
Product of Sums
2-4 Map Simplification
Two-Variable Map
Me-Variable Map
Four-Variable Map
2-5 Map Manipulation
Essential Prime Implicants
Nonessential Prime Implicants
Product-of Sums Simplification
Don't--Care Condihons
2-6 NAND and NOR Gates
NAND Circuits
Two-Level Implementation
Multi1evel NAND Circuits
NOR Circuits
2-7 Exclusive-OR Gates
Odd Function
Parity Generation and Checking
2-8 Integrated Circuits
Levels of Integration
Digital Logic Families
Positive and Negative Logic
Transmission Gates
2-9 Chapter Sununary
References
Problems
CHAPTER 3
COMBINATIONAL LOGIC DESIGN
3-1 Combinational Circuits
3-2 Design Topics
Design Hierarchy
Top-Down Design
Computer-Aided Design
Hardware Description Languages
Logic Synthesis
3-3 Analysis Procedure
Derivation of Boolean Functions
Derivation of the Truth Table
Logic Simulation
3-4  Design Procedure
Code Converters
3-5 Decoders
Decoder Expansion
Combinahonal Circuit Implemenation
3-6 Enceders
Priority Encoder
3-7 Multiplexers
Combinahonal Circuit Implementation
Demultiplexer
3-8 Binare Adders
Half Adder
Full Adder
Binare Ripple Carry Adder
Cap Lookahead Aduer
3-9 Binary Subtraction
Complements
Subtraction with Complements
3-10 Binary Adder-Subtractors
Signed Binary Numbers
Signed Binary Addition and Subtraction
Overflow
3-11 Binny Multipliers
3-12 Decimal Arithmetic
Use of Complements in Decimal
3-13 HDL Representations -- VHDL
Structural Description
Dataflow Description
Hierarchical Description
Behavioral Description
3-14 HDL Representations - Verilog
Structural Description
Dataflow Description
Hierarchical Description
Behavioral Description
3-15 Chapter Sununary
References
Problems
CHAPTER 4 183
SEQUENTIAL CIRCUITS
4-1 Sequential Circuit Definitions
4-2 Latches
SR and S R Latches
D Latch
4-3 Flip-Flops
Master-Slave Flip-Flop
Edge-Triggered Flip-Flop
Standard Graphics Symbols
Characteristic Tables
Direct Inputs
4-4 Sequential Circuit Analysis
Input Equations
State Table
Analysis with JK Flip-Flops
State Diagram
4-5 Sequential Circuit Design
Design Procedure
Finding State Diagrams and State Tables
4-6 Designing with D Flip-Flops
Designing with Unused States
4-7 Designing with JK Flip-Flops
Flip-Flop Excitation Tables
Design Procedure
4-8 HDL Representation for Sequential Circuits -- VHDL
4-9 HDL Representation for Sequential Circuits -- Verilog
4-10 References
Problems
CHAPTER 5 249
REGISTERS AND COLJNTERS
5-1 Definition of Register and Counter
5-2 Registers
Register with Parallel Load
5-3 Shift Registers
Serial Transfer
Serial Addition
Shift Register with Parallel Load
Bidirectional Shift Register
5-4 Ripple Counter
5-5 Synchronous Binary Counters
Design of Binary Counters
Counter with D Flip-Flops
Serial and Parallel Counters
Up-Down Binary Counter
Binary Counter with Parallel Load
5-6 Other Counters
BCD Counter
Arbitrary Count Sequence
5-7 HDL Representation for Shift Registers and Counters
5-8 HDL Representation for Shift Registers and Counters
5-9 Chapter Sununary
References
Problems
CHAPTER 6 285
MEMORY AND PROGRAMMABLE LOGIC DEVICES
6-1 Memory and Progranunable Logic Device
Definitions
6-2 Random-access Memory
Write and Read Operations
Timing Waveforms
Properties of Memory
6-3 RAM Integrated Circuits
Three-State Buffers
Coincident Selection
Dynamic RAM ICs
6-4 Array of RAM ICs
Arrays of Dynamic RAM ICs
6-5 Programmable Logic Technologies
6-6 Read--only Memory
Combinational Circuit Implementation
6-7 Programmable Logic Array
6-8 Programmable Array Logic Devices
6-9 VLSI Programmable Logic Devices
Altera MAX 7000 CPLDs
Xilinx XC4000 Structure
Xilinx Interconnections
Xilinx Logic
6-10 Chapter Sununary
References
Problems
CHAPTER 7 339
REGISTER TRANSFERS AND DATAPATHS
7-1 Datapaths and Operations
7-2 Register Transfer Operations
A Note For VHDL And Verilog Users Only
7-3 Microoperations
Arithmetic Microoperations
Logic Microoperations
Shift Microoperations
7-4 Multiplexer-based Transfer
7-5 Bus-based Transfer
Three-State Bus
Memory Transfer
7-6 Datapaths
7-7 The Arithmetic/Logic Unit
Anthmetic Circuit
Logic Circuit
Arithmetic/Logic Unit
7-8 The Shifter
Barrel Shifter
7-9 Datapath Representation
7-10 The Control Word
7-11 Pipelined Datapath
Execution of Pipeline Microoperations
7-12 Chapter Sununary
References
Problems
CHAPTER 8 391
SEQUENCING AND CONTOL
8-1 The Control Unit
8-2 Algorithmic State Machines
The ASM Chart
Timing Considerations
8-3 Design Example: Binary Multiplier
Binary Multiplier
Multiplier Datapath
ASM Chart for Multiplier
8-4 Hardwired Control
Sequence Register and Decoder
One Flip-Flop per State
8-5 HDL Representation of the Binary Multiplier - VHDL
8-6 HDL Representation of the Binary Multiplier - Verilog
8-7 Microprogranund Control
Binary Multiplier Example
8-8 A Simple Computer Architecture
Instructions
Instruction Formats
Storage Resource Diagram
8-9 Single-Cycle Hardwired Control
Instruction Decoder
Sample Instructions and Program
8-10 Multiple-Cycle Microprogranund Control
Microprogram Design
The Hardwired Alternative
8-11 Pipelined Control
Pipeline Programming and Performance
8-12 Chapter Summary
References
Problems
CHAPTER 9 467
INSTRUCTION SET ARCHITECTURE
9-1 Computer Architecture Concepts
Basic Computer Operation Cycle
Register Set
9-2 Operand Addressing
Three-address Instructions
Two-address Insmictions
One-address Instructions
Zero-address Instructions
Addressing Architectures
9-3 Addressing Modes
Implied Mode
Inundiate Mode
Register and Register-Indirect Modes
Direct Addressing Mode
Indirect Addressing Mode
Relative Addressing Mode
Indexed Addressing Mode
Summary of Addressing Modes
9-4 Insmiction Set Architectures
9-5 Data Transfer Instructions
Stack Instructions
Independent versus Memory-Mapped I/O
9-6 Data Manipulation Instructions
Arithmetic Instructions
Logical and Bit Manipulation Instructions
Shift Instructions
9-7 Floating-point Computations
Arithmetic Operations
Biased Exponent
Standard Operand Format
9-8 Program Control Instructions
Conditional Branch Instructions
Procedure Call and Return Instructions
9-9 Program Interrupt
Types of Interrupts
Processing External Interrupts
9-10 Chapter Sununary
References
Problems
CHAPTER l0 511
CENTRAL PROCESSING UNIT DESIGNS
10-1 Two CPU Designs
10-2 The Complex Instruction Set Computer
Insmiction Set Aichitecture
Datapath Organization
Microprogranuned Control Organization
Microprograrn Structure
Microroutines
10-3 The Reduced Instruction Set Computer
Instruction Set Architecture
Addressing Modes
Datapath Organization
Control Organization
Data Hazards
Control Hazards
10-4 More on Design
CISC-RISC Comparison
High-Performance CPU Concepts
Recent Architectural Innovations
Digital Systems
10-5 Chapter Summary
References
Problems
CHAPTER ll 575
INPUT-OUTPUT AND COMMUNICATION
11-1 Computer llO
11-2 Sample Peripherals
Keyboard
Hard Disk
Gmphics Display
I/O Transfer Rates
11-3 I/O Interfaces
I/O Bus and Interface Unit
Example of I/O Interface
Strobing
Handshaking
11-4 Serial Communicahon
Asynchronous Transmission
Synchronous Transmission
The Keyboard Revisited
A Packet-Based Serial I/O Bus
11-5 Modes of Transfer
Example of Program-Controlled Thosfer
Interrupt-Initiated Transfer
11-6 Priority Interrupt
Daisy Chain Priority
Parallel Priority Hardware
11-7 Direct Memory Access
DMA Controller
DMA Transfer
11-8 I/O Processors
11-9 Chapter Summary
References
Prob1ems
CHAPTER l2 613
MEMOR SYSTEMS
12-1 Memory Hierarchy
12-2 Locality of Reference
12-3 Cache Memory
Cache Mappings
Line Size
Cache Loading
Write Methods
Integration of Concepts
Instruction and Data Caches
Multiple-Level Caches
12-4 Virtual Memory
Page Tables
Translation Lookaside Buffer
Vinual Memory and Cache
12-5 Chapter Sununary
References
Problems
INDEX 643