數(shù)字設(shè)計(jì)：原理與實(shí)踐（影印版）

CONTENTS
FOREWORDXV
PREFACExvii
1INTRODUCTION
1.1AboutDigitalDesign
1.2AnalogversusDigital
1.3DigitalDevices
1.4ElectronicAspectsofDigitalDesign
1.5SoftwareAspectsofDigitalDesign
1.6IntegratedCircuits
1.7ProgrammableLogicDevices
1.8Application-SpecificICs
1.9Printed－CircuitBoards
1.10Digital-DesignLevels
1.11TheNameoftheGame
1.12GoingForward
DrillProbbems
2NUMBERSYSTEMSANDCODES
2.1PositionalNumberSystems
2.2OctalandHexadcimalNumbers
2.3GeneralPositional－Number－SystemConversions
2.4AdditionandSubtractionofNondecimalNumbers
2.5RepresentationofNegativeNumbers34
2.5.1Signed－MagnitudeRepresentation
2.5.2ComplementNumberSystems
2.5.3Radix－ComplementRepresentation
2.5.4Two's－ComplementRepresentation
2.5.5DiminishedRadix-ComplementRepresentation
2.5.6One's－ComplementRepresentation2.5.7ExcessRepresentations
2.6Two's－ComplementAdditionandSubtaction
2.6.1AdditionRules
2.6.2AGraphicalView
2.6.3Overflow
2.6.4SubtractionRules
2.6.5Two's－ComplementandUnsignedBinaryNumbers
2.7Ones'－ComplementAdditionandSubtraction
2.8BinaryMultiplication
2.9BinaryDivision
2.10BinaryCodesforDecimalNumbers
2.11GrayCode
2.12CharacterCodes
2.13CodesforActions,Conditions,andStates
2.14n-CubesandDistance
2.15CodesforDetectingandCorrectingErrors
2.15.1Error－DetectingCodes
2.15.2Error－CorrectingandMultiple－Error－DetectingCodes
2.15.3HammingCodes
2.15.4CRCCodes
2.15.5Two-DimensionalCodes
2.15.6ChecksumCodes
2.15.7m－cut-of-nCodes
2.16CodesforSerialDataTransmissionandStorage
2.16.1ParallelandSerialData
2.16.2SerialLineCodes
References
DrillProblems
Exercises
3DIGITALCIRCUITS
3.1LogicSignalsandGates
3.2LogicFamilies
3.3CMOSLogic
3.3.1CMOSLogicLevels
3.3.2MOSTransistors
3.3.3BasicCMOSInverterCircuit
3.3.4CMOSNANDandNORGates
3.3.5Fan－In
3.3.6NoninvertingGates
3.3.7CMOSAND－OR-INVERTandOR－AND－INVERTGates
3.4ElectricalBehaviorofCMOSCircuits
3.4.1Overiew
3.4.2DataSheetsandSpecifications
3.5CMOSSteady-StateElectricalBehavior
3.5.1LogicLevelsandNoiseMangins
3.5.2CircuitBehaviorwithResistiveLoads
3.5.3CircuitBehaviorwithNonidealInputs
3.5.4Fanout
3.5.5EffectsofLoading
3.5.6UnusedInputs
3.5.7CurrentSpikesandDecouplingCapacitors
3.5.8HowtoDestroyaCMOSDevice
3.6CMOSDynamicElectricalBehavior
3.6.1TransitionTime
3.6.2PropagationDelay
3.6.3PowerConsumption
3.7OtherCMOSInputandOutputStructures
3.7.1TransmissionGates
3.7.2Schmitt－TriggerInputs
3.7.3Three－StateOutputs
3.7.4Open－DrainOutputs
3.7.5DrivingLEDs
3.7.6MultisourceBuses
3.7.7WiredLogic
3.7.8Pull-UpResistors
3.8CMOSLogicFamilies
3.8.1HCandHCT3.8.2VHCandVHCT
3.8.3HC,HCT,VHC,andVHCTElectricalCharacteCharacteristics
3.8.4FCTandFCT－T
3.8.5FCT-TElectricalCharacteristics
3.9BipolarLogic
3.9.2Diodes
3.9.2DiodeLogic
3.9.3BipolarJunctionTransistors
3.9.4TransistorLogicInverter
3.9.5SchottkyTransistors
3.10Transistor-Transistor-Logic
3.10.1BasicTTLNANDGate
3.10.2LogicLevelsandNoiseMaryins
3.10.3Fanout
3.10.4UnusedInputs
3.10.5AdditionalTTLGateTypes
3.11TTLFamilies
3.11.1EarlyTTLFamilies
3.11.2SchottkyTTLFamilies
3.11.3CharacteristicsofTTLFamilies
3.11.4ATTLDataSheet
3.12CMOS/TTLInterfacing
3.13Low－VoltageCMOSLogicandInterfacing
3.13.13.3－VLVTTLandLVCMOSLogic
3.13.25－VTolerantInputs
3.I3.35－VTolerantOutputs
3.13.3TTL/LVTTLInterfacingSummary
3.13.52.5－Vand1.8－VLogic
3.14Emitter-CoupledLogic
3.14.1BasicCMLCircuit
3.14.2ECL10K/10HFamilies
3.14.3ECL100KFamily
3.14.4PositiveECL（PECL）
References
DrillProblems
EXercises
4COMBINATIONALLOGICDESIGNPRINCIPLES
4.1SwitchingAlgebra
4.1.1Axioms
4.1.2Single－VariableTheorems
4.1.3Two-andThree-VariableTheorems
4.1.4n－VariableTheorems
4.1.5Duality
4.1.6StandardReprentationsofLogicFunctions
4.2Combinational－CircuitAnalysis
4.3Combinational－CircuitSynthesis
4.3.1CinuitDescriptionsandDesigns
4.3.2CircuitManipulations
4.3.3Combinational－CircuitMinimization
4.3.4KarnaughMaps
4.3.5MinimizingSumsofProducts
4.3.6SimplifyingProductsofSums
4.3.7“Don't－Care”InputCombinations
4.3.8Multiple_OutputMinimization
4.4ProgrammedMinimizationMethods
4.4.1RepresentationofProductTerms
4.4.2FindingPrimeImplicantsbyCombiningProductTerms
4.4.3FindingaMinimalCoverUsingaPrime－ImplicantTable
4.4.4OtherMinimizationMethods
4.5TimingHazards
4.5.1StaticHazards
4.5.2FindingStaticHazardsUsingMaps
4.5.3DynamicHazards
4.5.4DesigningHazard－FreeCircuits
4.6TheABELHardwareDescriptionLanguage
4.6.1ABELProgramStructure
4.6.2ABELComplierOperation
4.6.3WHENStatementsandEquationBlocks
4.6.4TruthTables
4.6.5Ranges,Sets,andRelations
4.6.6Don’t－CareInputs
4.6.7TestVectors
4.7TheVHDLHardwareDescriptionLanguage
4.7.1DesignFlow
4.7.2ProgramStructure
4.7.3TypesandConstants
4.7.4FunctionsandProcedures
4.7.5LibrariesandPackages
4.7.6StrucralDesignElements
4.7.7DataflowDesignElements
4.7.8BehavioralDesignElements
4.7.9TheTimeDimensionandSimulation
4.7.10Synthesis
References
DrillProblems
Exercises
5COMBINATIONALLOGICDESIGNPRACTICES
5.1DocumentstionStandards
5.1.1BlockDiagrams
5.1.2GateSymbols
5.1.3SignalNamesandActiveLevels
5.1.4ActiveLevelsforPins
5.1.5Bubble－to－BubbleLogicDesign
5.1.6DrawingLayout
5.1.7Buses
5.1.8AdditionalSchematicInformation
5.2CircuitTiming
5.2.1TimingDiagrams
5.2.2PropogationDelay
5.2.3TimingSpecifications
5.2.4TimingAnalysis
5.2.5TimingAnalysisTools
5.3CombinationalPLDs
5.3.1ProgrammableLogicArrays
5.3.2ProgrammableArrayLogicDevices
5.3.3GenericArrayLogicDevices
5.3.4BipolarPLDCircuits
5.3.5CMOSPLDCircuits
5.3.6DeviceProgrammingandTesting
5.4Decoders
5.4.1BinaryDecoders
5.4.2LogicSymbolsforLarger－ScaleElements
5.4.3The74x139Dual2-to-4Decoder
5.4.4The74xI383－to-8Decoder
5.4.5CascadingBinaryDecoders
5.4.6DecodersinABELandPLDs
5.4.7DecodersinVHDL
5.4.8Seven－SegmentDecoders
5.5Encoders
5.5.1PriorityEncoders
5.5.2The74x148PriorityEncoder
5.5.3EncodersinABELandPLDs
5.5.4EncodersinVHDL
5.6Three-StateDevices
5.6.1Three－StateBuffers
5.6.2StandardSSIandMSIThree-StateBuffers
5.6.3Three－StateOutputsinABELandPLDs
5.6.4Three-StateOutputsinVHDL
5.7Multiplexers
5.7.1StandardMSIMultiplexers
5.7.2EXpandingMultiplexers
5.7.3Multiplexers,Demultiplexers,andBuses
5.7.4MultiplexersinABELandPLDs
5.7.5MultiplexersinVHDL
5.8Exclusive－ORGatesandPartyCircuits
5.8.1Exclusive－ORandExclusive－NORGates
5.8.2ParityCircuits
5.8.3The74x2809－BitParityGenerator
5.8.4Parity-CheckingApplications
5.8.5Exclusive－ORGatesandParityCircuitsinABELandPLDs
5.8.6Exclusive－ORGatesandParityCircuitsinVHDL
5.9Comparators
5.9.1ComparatorStructure
5.9.2lterativeCircuits
5.9.3AnIierativeComparatorCircuit
5.9.4StandardMSIComparators
5.9.5ComparatorsinABELandPLDs
5.9.6ComparatorsinVHDL
5.10Adders,Subtractors,andALUs
5.10.1HalfAddersandFullAdders
5.10.2RippleAdders
5.10.3Subtractors
5.10.4CarryLookaheadAdders
5.10.5MSIAdders
5.10.6MSIArithmeticandLogicUnits
5.10.7Group－CarryLooKahead
5.10.8AddersinABELandPLDs
5.10.9AddersinVHDL
5.11CombinationalMultipliers
5.11.1CombinationalMultiplierStructures
5.11.2MultiplicationinABELandPLDs
5.11.3MultiplicationinVHDL
References
DrillProblems
Exercises
6COMBNATIONAL－CIRCUITDESIGNEXAMPLES
6.1Buiding－BlockDesignExamples
6.1.1BarrelShifter
6.1.2SimpleFloating－PointEncoder
6.1.3Dual-PriorityEncoder
6.1.4CascadinmpComparators
6.1.5Mode－DependentComparator
6.2DesignExamplesUsingABELandPLDs
6.2.1BarrelShifter
6.2.2SimpleFloating－PointEncoder
6.2.3Dual－PriorityEncoder
6.2.4CascadingComparators
6.2.5Mode－DependentComparator
6.2.6OnesCounter
6.2.7Tic－Tac－Toe
6.3DesignExamplesUsingVHDL
6.3.1BarrelShifter
6.3.2SimpleFloating－PointEncoder
6.3.3Dual-PriorityEncoder
6.3.4CascadingComparators
6.3.5Mode－DependentComparator
6.3.6OnesCounter
6.3.7Tic-Tac-Toe
Exercises
7SEQUENTIALLOGICDESIGNPRINCIPLES
7.1BistableElements
7.1.1DigilaIAnalysis
7.1.2AnalogAnalysis
7.1.3MetastableBehavior
7.2LatchesandFlip－Flops
7.2.1S-RLatch
7.2.2S-RLatch
7.2.3S-RLatchwithEnable
7.2.4DLatch
7.2.5Edge－TriggeredDFlip－Flop
7.2.6Edge－TriggeredDFlip－FlopwithEnable
7.2.7ScanFlip－Flop
7.2.8Master／SlaveS－RFlip－Flop
7.2.9Master／SlaveJ-KFlip-Flop
7.2.10Edge-TriggeredJ-KFlip-Flop
7.2.11TFlip-Flop
7.3ClockedSynchronousState－MachineAnalysis
7.3.1State－MachineStructure
7.3.2OutputLogic
7.3.3CharacteristicEquations
7.3.4AnalysisofStateMachineswithDFlip－Flops
7.3.5AnalysisofStateMachineswithJ－KFlip－Flops
7.4ClockedSynchronousState－MachineDesign
7.4.1State－TableDesignExample
7.4.2StateMinimization
7.4.3StateAssignment
7.4.4SynthesisUsingDFlip－Flops
7.4.5SynthesisUsingJ-KFlip－Flops
7.4.6MoreDesignExamplesUsingDFlip－Flops
7.5DesigningStateMachinesUsingStateDiagrams
7.6State－MachineSynthesisUsingTransitionLists
7.6.1TransitionEquations
7.6.2ExcitationEquations
7.6.3VariationsontheScheme
7.6.4RedlizingtheStateMachine
7.7AnotherState－MachineDesignExample
7.7.1TheGuessingGame
7.7.2UnusedStates
7.7.3Output－CodedStateAssignment
7.7.4“Don't－Care”StateCodings
7.8DecomposingStateMachines
7.9FeedbackSequentialCircuits
7.9.1Analysis
7.9.2AnalyzingCircuitswithMultipleFeedbackLoops
7.9.1Races
7.9.4StateTablesandFlowTables
7.9.5CMOSDFliP－FlopAnalysis
7.10FeedbackSequential－CircuitDesign
7.10.1Latches
7.10.2DesigningFundamental－ModeFlowTable
7.10.3Flow－TableMinimization
7.10.4Race－FreeStateAssignment
7.10.5ExcitationEquations
7.10.6EssentialHazards
7.10.7Summary
7.11ABELSequential－CircuitDesignFeatures
7.11.1RegisteredOutputs
7.11.2StateDiagrams
7.11.3ExternalStateMemory
7.11.4SpecifyingMooreOutputs
7.11.5SpecifyingMealyandPipelinedOutputswithWITH
7.11.6TestVectors
7.12VHDLSequential-CircuitDesignFeatures
7.12.1FeedbackSequentialCircuits
7.12.2ClockedCircuits
References
DrillProblems
Exercises
8SEQUENTIALLOGICDESIGNPRACTICES
8.1Sequential-CircuitDocumentationStandards
8.1.1GeneralRequirements
8.1.2LogicSymbols
8.1.3State－MachineDescriptions
8.1.4TimingDiagramsandSpecifications
8.2LatchesandFlip-Flops
8.2.1SSILatchesandFlip-Flops
8.2.2SwitchDebouncing
8.2.3TheSimplestSwitchDebouncer
8.2.4BusHolderCircuit
8.2.5MultibitRegistersandLatches
8.2.6RegistersandLatchesinABELandPLDs
8.2.7RegistersandLatchesinVHDL
8.3SequentialPLDs
8.3.1BipolarSequentialPLDs
8.3.2SequentialGALDevices
8.3.3PLDTimingSpecifications
8.4Counters
8.4.1RippleCounters
8.4.2SynchronousCounters
8.4.3MSICountersandApplications
8.4.4DecodingBinary-CounterStates
8.4.5CountersinABELandPLDs
8.4.6CountersinVHDL
8.5ShiftRegisters
8.5.1Shift－RegisterStructure
8.5.2MSIShittRegisters
8.5.3TheWorld'sBiggestShift－RegisterApplication
8.5.4Serial/ParallelConversion
8.5.5Shift－RegisterCounters
8.5.6RingCounters
8.5.7JohnsonCounters
8.5.8LinearFeedbackShift－RegisterCounters
8.5.9ShiftRegistersinABELandPLDs
8.5.10ShiftRegistersinVHDL
8.6IterativeversusSequentialCircuits
8.7SynchronousDesignMethodology
8.7.1SynchronousSystemStructure
8.7.2ASynchronousSystemDesignExample
8.8ImpedimentstoSynchronousDesign
8.8.1ClockSkew
8.8.2GatingtheClock
8.8.3AsynchronousInputs
8.9SynchronizerFailureandMetastability
8.9.1SynchronizerFailure
8.9.2MetastabilityResolutionTime
8.9.3ReliableSynchronizerDesign
8.9.4AnalysisofMetastableTiming
8.9.5BetterSynchronizers
8.9.6OtherSynchronizerDesigns
8.9.7Metastable－HardenedFlip－Flops
8.9.8SynchronizingHig-SpeedDataTransfers
References
DrillProblems
Exercises
9SEQUENTIAL－CIRCUITDESIGNEXAMPLES
9.1DesignExamplesUsingABELandPLDs
9.1.1TimingandPackagingofPLD-BasedStateMachines
9.1.2AFewSimpleMachines
9.1.3T-BirdTailLights
9.1.4TheGuessingGame
9.1.5ReinventingTraffic-LightControllers
9.2DesignExamplesUsingVHDL
9.2.1AFewSimpleMachines
9.2.2T-BirdTailLights
9.2.3TheGuessingGame
9.2.4ReinventingTraffic-LightControllers
Exercises
10MEMORY,CPLDS,ANDFPGAS
10.1Read－OnlyMemory
10.1.1UsingROMsfor“Random”CombinationalLogicFunctions
10.1.2InternalROMStructure
10.1.3Two－DimensionalDecoding
10.1.4CommercialROMTypes
10.1.5ROMControlInputsandTiming
10.1.6ROMApplications
10.2Read／WriteMemory
10.3StaticRAM
10.3.1Static-RAMInputsandOutputs
10.3.2Static－RAMInternalStructure
10.3.3Static－RAMTiming
10.3.4StandardStaticRAMs
10.3.5SynchronousSRAM
10.4DynamicRAM
10.4.1Dynamic－RAMStructure
10.4.2Dynamic－RAMTiming
10.4.3SynchronousDRAMs
10.5ComplexProgrammableLogicDevices
10.5.1XilinxXC9500CPLDFamily
10.5.2Function－BiockArchitecture
10.5.3Input/Output-BiockArchitecture
10.5.4SwitchMatrix
10.6Field-ProgrammableGateArrays
10.6.1XilinxXC4000FPGAFamily
10.6.2ConfigurableLogicBlock
10.6.3Input／OutpotBlock
10.6.4ProgrammableInterconnect
References
DrillProblems
Exercises
11ADDITIONALREAL-WORLDTOPICS
11.1Computer-AidedDesignTools
11.1.1HardwareDescriptionLanguages
11.1.2SchematicCapture
11.1.3TimingDrawingsandSpecifications
11.1.4CircuitAnalysisandSimulation
11.1.5PCBLayout
11.2DesignforTestability
11.2.1Testing
11.2.2Bed－of-NailsandIn－CircuitTesting
11.2.3ScanMethods
11.3EstimatingDigitalSystemReliablity
11.3.1FailureRates
11.3.2ReliabilityandMTBF
11.3.3SystemReliability
11.4TransmissionLines,Reflections,andTermination
11.4.1BasicTransmission－LineTheory
11.4.2Logic－SignalInterconnectionsasTransmissionLines
11.4.3Logic－SignalTerminations
References
INDEX