嵌入式系統設計

Preface
Acknowledgments
1. INTRODUCTION
1.1 Terms and scope
1.2 Application areas
1.3 Growing importance of embedded systems
1.4 Structure of this book
2. SPECIFICATIONS
2.1 Requirements
2.2 Models of computation
2.3 StateCharts
2.3.1 Modeling of hierarchy
2.3.2 Timers
2.3.3 Edge labels and StateCharts semantics
2.3.4 Evaluation and extensions
2.4 General language characteristics
2.4.1 Synchronous and asynchronous languages
2.4.2 Process concepts
2.4.3 Synchronization and communication
2.4.4 Specifying timing
2.4.5 Using non-standard I/O devices
2.5 SDL
2.6 Petri nets
2.6.1 Introduction
2.6.2 Condition/event nets
2.6.3 Place/transition nets
2.6.4 Predicate/transition nets
2.6.5 Evaluation
2.7 Message Sequence Charts
2.8 UML
2.9 Process networks
2.9.1 Task graphs
2.9.2 Asynchronous message passing
2.9.3 Synchronous message passing
2.10 Java
2.11 VHDL
2.11.1 Introduction
2.11.2 Entities and architectures
2.11.3 Multi-valued logic and IEEE 1164
2.11.4 VHDL processes and simulation semantics
2.12 SystemC
2.13 Verilog and SystemVerilog
2.14 SpecC
2.15 Additional languages
2.16 Levels of hardware modeling
2.17 Language comparison
2.18 Dependability requirements
3. EMBEDDED SYSTEM HARDWARE
3.1 Introduction
3.2 Input
3.2.1 Sensors
3.2.2 Sample-and-hold circuits
3.2.3 A/D-converters
3.3 Communication
3.3.1 Requirements
3.3.2 Electrical robustness
3.3.3 Guaranteeing real-time behavior
3.3.4 Examples
3.4 Processing Units
3.4.1 Overview
3.4.2 Application-Specific Circuits （ASICs）
3.4.3 Processors
3.4.4 Reconfigurable Logic
3.5 Memories
3.6 Output
3.6.1 D/A-converters
3.6.2 Actuators
4. EMBEDDED OPERATING SYSTEMSMIDDLEWARE, AND SCHEDULING
4.1 Prediction of execution times
4.2 Scheduling in real-time systems
4.2.1 Classification of scheduling algorithms
4.2.2 Aperiodic scheduling
4.2.3 Periodic scheduling
4.2.4 Resource access protocols
4.3 Embedded onerating systems
4.3.1 General requirements
4.3.2 Real-time operating systems
4.4 Middleware
4.4.1 Real-time data bases
4.4.2 Access to remote objects
5. IMPLEMENTING EMBEDDED SYSTEMS:HARDWARE/SOFTWARE CODESIGN
5.1 Task level concurrency management
5.2 High-level optimizations
5.2.1 Floating-point to fixed-point conversion
5.2.2 Simple loop transformations
5.2.3 Loop tiling/blocking
5.2.4 Loop splitting
5.2.5 Array folding
5.3 Hardware/software partitioning
5.3.1 Introduction
5.3.2 COOL
5.4 Compilers for embedded systems
5.4.1 Introduction
5.4.2 Energy-aware compilation
5.4.3 Compilation for digital signal processors
5.4.4 Compilation for multimedia processors
5.4.5 Compilation for VLIW processors
5.4.6 Compilation for network processors
5.4.7 Compiler generation, retargetable compilersand design space exploration
5.5 Voltage Scaling and Power Management
5.5.1 Dynamic Voltage Scaling
5.5.2 Dynamic power management （DPM）
5.6 Actual design flows and tools
5.6.1 SpecC methodology
5.6.2 IMEC tool flow
5.6.3 The COSYMA design flow
5.6.4 Ptolemy II
5.6.5 The OCTOPUS design flow
6. VALIDATION
6.1 Introduction
6.2 Simulation
6.3 Rapid Prototyping and Emulation
6.4 Test
6.4.1 Scope
6.4.2 Design for testability
6.4.3 Self-test programs
6.5 Fault simulation
6.6 Fault injection
6.7 Risk- and dependability analysis
6.8 Formal Verification
References
About the author
List of Figures
Index