時鐘發(fā)生器在片上系統(tǒng)處理器中的應(yīng)用

ABOUT THE AUTHOR
PREFACE
FOREWORD
1.INTRODUCTION
1.1 WHAT ARE SYSTEM-ON-A-CHIP PROCESSORS?
1.2 ORGANIZATION
2.PHASE-LOCKED LOOP FUNDAMENTALS
2.1 Introduction
2.2 PLL Basics
2.3 Continuoas-time Linear Analysis of PLLs
2.4 Discrete-time Linear Analysis of PLLs
2.5 Nonlinear Locking Behaviour of PLLs
2.6 Summary
3.LOW-VOLTAGE ANALOG CMOS DESIGN
3.1 Introduction
3.2 MOS Transistors
3.3 Low-Voltage Current Mirrors
3.4 Low- Voltage Charge Pumps
3.5 Low- Voltage Oscillator Design
3.6 Voltage and Current References
3.7 Summary
4.JITTER ANALYSIS IN PHASE-LOCKED LOOPS
4.1 Introduction
4.2 Jitter Basics
4.3 Jitter in Voltage Controlled Oscillators
4.4 Jitter Performance of Closed-Loop PLL System
4.5 Coupling Noise Effects on Jitter
4.6 Summary
5.LOW-JITTER PLL ARCHITECTURES
5.1 Introduction
5.2 Differential PLL Architecture.
5.3 Supply Voltage Regulated PLL Architectures
5.4 Adaptive PLL Architectures
5.5 Resistorless Loop Filter PLLs
5.6 Delay-Locked Loop Frequency Multipliers
5.7 Summary
6.DIGITAL PLL DESIGN
6.1 Introduction
6.2 Basic Topology
6.3 Z-domain Analysis
6.4 Circuit Implementation Issues
6.5 Alternate Digital PLL for Clock Generation
6.6 Summary
7.DSP CLOCK GENERATOR ARCHITECTURES
7.1 Introduction
7.2 Sampling Clock Requirements for Data Converters
7.3 Jitter in Frequency Dividers
7.4 Fractional-N PLLs as Clock Generators
7.5 Oversampled PLL Topologies
7.6 Direct Digital Synthesis with Analog Interpolation
7.7 Summary
8.DESIGN FOR TESTABILITY IN PLLS
8.1 Introduction
8.2 Verification of SoC PLLs
8.3 Jitter Measurement Techniques
8.4 Design for Testability and Self-Test in PLLs
8.5 Summary
9.CLOCK PARTITIONING AND SKEW CONTROL
9.1 Introduction
9.2 Clock Distribution Networks in SoCs
9.3 Performance Limitations in Clock Networks
9.4 Active Skew Management Strategies
9.5 Multi-phase Clock Generator
9.6 Low-Power Clock Distribution Strategies
9.7 Multi-clock Domain Interfacing
9.8 Summary
INDEX