模擬電路版圖的藝術(shù)（第二版 英文版）

Contents
目 錄
Chapter 1 Device Physics 器件物理… ………………………………………………………1
1．1 Semiconductors 半導(dǎo)體 ……………………………………………………………………1
1．1．1 Generation and Recombination 產(chǎn)生與復(fù)合 ………………………………………………………4
1．1．2 Extrinsic Semiconductors 非本征（雜質(zhì)）半導(dǎo)體 …………………………………………………6
1．1．3 Diffusion and Drift 擴(kuò)散和漂移 ……………………………………………………………………9
1．2 PN Junctions PN結(jié) ……………………………………………………………………11
1．2．1 Depletion Regions 耗盡區(qū) …………………………………………………………………………11
1．2．2 PN Diodes PN結(jié)二極管 …………………………………………………………………………13
1．2．3 Schottky Diodes 肖特基二極管 …………………………………………………………………16
1．2．4 Zener Diodes 齊納二極管 …………………………………………………………………………18
1．2．5 Ohmic Contacts 歐姆接觸 …………………………………………………………………………19
1．3 Bipolar Junction Transistors 雙極型晶體管 ……………………………………………21
1．3．1 Beta β值 …………………………………………………………………………………………23
1．3．2 I-V Characteristics I-V特性 ………………………………………………………………………24
1．4 MOS Transistors MOS晶體管 …………………………………………………………25
1．4．1 Threshold Voltage 閾值電壓 ………………………………………………………………………27
1．4．2 I-V Characteristics I-V特性 ………………………………………………………………………29
1．5 JFET Transistors JFET晶體管 …………………………………………………………32
1．6 Summary 小結(jié) …………………………………………………………………………34
1．7 Exercises 習(xí)題 …………………………………………………………………………35
Chapter 2 Semiconductor Fabrication 半導(dǎo)體制造 …………………………………… 37
2．1 Silicon Manufacture 硅制造 ……………………………………………………………37
2．1．1 Crystal Growth 晶體生長(zhǎng) …………………………………………………………………………38
2．1．2 Wafer Manufacturing 晶圓制造 …………………………………………………………………39
2．1．3 The Crystal Structure of Silicon 硅的晶體結(jié)構(gòu) …………………………………………………39
2．2 Photolithography 光刻技術(shù) ……………………………………………………………41
2．2．1 Photoresists 光刻膠 ………………………………………………………………………………41
2．2．2 Photomasks and Reticles 光掩模和掩模版 ………………………………………………………42
2．2．3 Patterning 光刻 ……………………………………………………………………………………43
2．3 Oxide Growth and Removal 氧化物生長(zhǎng)和去除 ………………………………………43
2．3．1 Oxide Growth and Deposition 氧化物生長(zhǎng)和淀積 ………………………………………………44
2．3．2 Oxide Removal 氧化物去除 ………………………………………………………………………45
2．3．3 Other Effects of Oxide Growth and Removal 氧化物生長(zhǎng)和去除的其他效應(yīng) …………………47
2．3．4 Local Oxidation of Silicon (LOCOS) 硅的局部氧化 ……………………………………………49
2．4 Diffusion and Ion Implantation 擴(kuò)散和離子注入 ………………………………………50
2．4．1 Diffusion 擴(kuò)散 ……………………………………………………………………………………51
2．4．2 Other Effects of Diffusion 擴(kuò)散的其他效應(yīng)………………………………………………………53
2．4．3 Ion Implantation 離子注入 ………………………………………………………………………55
2．5 Silicon Deposition and Etching 硅淀積和刻蝕 …………………………………………57
2．5．1 Epitaxy 外延 ………………………………………………………………………………………57
2．5．2 Polysilicon Deposition 多晶硅淀積 ………………………………………………………………59
2．5．3 Dielectric Isolation 介質(zhì)隔離 ……………………………………………………………………60
2．6 Metallization 金屬化 ……………………………………………………………………62
2．6．1 Deposition and Removal of Aluminum 鋁淀積及去除 …………………………………………63
2．6．2 Refractory Barrier Metal 難熔阻擋金屬 …………………………………………………………65
2．6．3 Silicidation 硅化 …………………………………………………………………………………67
2．6．4 Interlevel Oxide， Interlevel Nitride， and Protective Overcoat
夾層氧化物，夾層氮化物和保護(hù)層 ………………………………………………………………69
2．6．5 Copper Metallization 銅金屬化 …………………………………………………………………71
2．7 Assembly 組裝 …………………………………………………………………………73
2．7．1 Mount and Bond 安裝與鍵合 ……………………………………………………………………74
2．7．2 Packaging 封裝 ……………………………………………………………………………………77
2．8 Summary 小結(jié) …………………………………………………………………………78
2．9 Exercises 習(xí)題 …………………………………………………………………………78
Chapter 3 Representative Processes 典型工藝 ………………………………………80
3．1 Standard Bipolar 標(biāo)準(zhǔn)雙極工藝 ………………………………………………………81
3．1．1 Essential Features 本征特性 ………………………………………………………………………81
3．1．2 Fabrication Sequence 制造順序 …………………………………………………………………82
3．1．3 Available Devices 可用器件 ………………………………………………………………………86
3．1．4 Process Extensions 工藝擴(kuò)展 ……………………………………………………………………93
3．2 Polysilicon-Gate CMOS 多晶硅柵CMOS工藝 ………………………………………96
3．2．1 Essential Features 本質(zhì)特征 ………………………………………………………………………97
3．2．2 Fabrication Sequence 制造順序 …………………………………………………………………98
3．2．3 Available Devices 可用器件 ………………………………………………………………………104
3．2．4 Process Extensions 工藝擴(kuò)展 ……………………………………………………………………109
3．3 Analog BiCMOS 模擬BiCMOS ………………………………………………………114
3．3．1 Essential Features 本質(zhì)特征 ……………………………………………………………………115
3．3．2 Fabrication Sequence 制造順序 …………………………………………………………………116
3．3．3 Available Devices 可用器件 ………………………………………………………………………121
3．3．4 Process Extensions 工藝擴(kuò)展 ……………………………………………………………………125
3．4 Summary 小結(jié) …………………………………………………………………………130
3．5 Exercises 習(xí)題 …………………………………………………………………………131
Chapter 4 Failure Mechanisms 失效機(jī)制… ………………………………………………133
4．1 Electrical Overstress 電過(guò)應(yīng)力 …………………………………………………………133
4．1．1 Electrostatic Discharge (ESD) 靜電漏放 …………………………………………………………134
4．1．2 Electromigration 電遷徙 …………………………………………………………………………136
4．1．3 Dielectric Breakdown 介質(zhì)擊穿 …………………………………………………………………138
4．1．4 The Antenna Effect 天線效應(yīng) ……………………………………………………………………141
4．2 Contamination 玷污 ……………………………………………………………………143
4．2．1 Dry Corrosion 干法腐蝕 …………………………………………………………………………144
4．2．2 Mobile Ion Contamination 可動(dòng)離子玷污 ………………………………………………………145
4．3 Surface Effects 表面效應(yīng) ………………………………………………………………148
4．3．1 Hot Carrier Injection 熱載流子注入 ………………………………………………………………148
4．3．2 Zener Walkout 齊納蠕變 …………………………………………………………………………151
4．3．3 Avalanche-Induced Beta Degradation 雪崩誘發(fā)β衰減 …………………………………………153
4．3．4 Negative Bias Temperature Instability 負(fù)偏置溫度不穩(wěn)定性 ……………………………………154
4．3．5 Parasitic Channels and Charge Spreading 寄生溝道和電荷分散 ………………………………156
4．4 Parasitics 寄生效應(yīng) ……………………………………………………………………164
4．4．1 Substrate Debiasing 襯底去偏置 …………………………………………………………………165
4．4．2 Minority-Carrier Injection 少子注入 ……………………………………………………………169
4．4．3 Substrate Influence 襯底效應(yīng) ……………………………………………………………………180
4．5 Summary 小結(jié) …………………………………………………………………………183
4．6 Exercises 習(xí)題 …………………………………………………………………………183
Chapter 5 Resistors 電阻 ……………………………………………………………………185
5．1 Resistivity and Sheet Resistance 電阻率和方塊電阻（薄層電阻） …………………185
5．2 Resistor Layout 電阻版圖 ………………………………………………………………187
5．3 Resistor Variability 電阻變化 ……………………………………………………………191
5．3．1 Process Variation 工藝變化 ………………………………………………………………………191
5．3．2 Temperature Variation 溫度變化 …………………………………………………………………192
5．3．3 Nonlinearity 非線性 ………………………………………………………………………………193
5．3．4 Contact Resistance 接觸電阻 ……………………………………………………………………196
5．4 Resistor Parasitics 電阻的寄生效應(yīng) ……………………………………………………197
5．5 Comparison of Available Resistors 不同電阻類型的比較 ……………………………200
5．5．1 Base Resistors 基區(qū)電阻 …………………………………………………………………………200
5．5．2 Emitter Resistors 發(fā)射區(qū)電阻 ……………………………………………………………………201
5．5．3 Base Pinch Resistors 基區(qū)埋層電阻 ………………………………………………………………202
5．5．4 High-Sheet Resistors 高值薄層電阻 ………………………………………………………………202
5．5．5 Epi Pinch Resistors 外延埋層電阻 ………………………………………………………………205
5．5．6 Metal Resistors 金屬電阻 …………………………………………………………………………206
5．5．7 Poly Resistors 多晶硅電阻 ………………………………………………………………………208
5．5．8 NSD and PSD Resistors NSD和PSD電阻 ………………………………………………………211
5．5．9 N-Well Resistors N阱電阻 ………………………………………………………………………211
5．5．10 Thin-Film Resistors 薄膜電阻 ……………………………………………………………………212
5．6 Adjusting Resistor Values 調(diào)整電阻阻值 ………………………………………………213
5．6．1 Tweaking Resistors 調(diào)節(jié)電阻 ……………………………………………………………………213
5．6．2 Trimming Resistors 微調(diào)電阻 ……………………………………………………………………216
5．7 Summary 小結(jié) …………………………………………………………………………223
5．8 Exercises 習(xí)題 …………………………………………………………………………224
Chapter 6 Capacitors and Inductors 電容和電感… ………………………………………226
6．1 Capacitance 電容 ………………………………………………………………………226
6．1．1 Capacitor Variability 電容的變化 …………………………………………………………………232
6．1．2 Capacitor Parasitics 電容的寄生效應(yīng) ……………………………………………………………235
6．1．3 Comparison of Available Capacitors 電容比較 …………………………………………………237
6．2 Inductance 電感 …………………………………………………………………………246
6．2．1 Inductor Parasitics 電感寄生效應(yīng) …………………………………………………………………248
6．2．2 Inductor Construction 電感的制作 ………………………………………………………………250
6．3 Summary 小結(jié) …………………………………………………………………………252
6．4 Exercises 習(xí)題 …………………………………………………………………………253
Chapter 7 Matching of Resistors and Capacitors 電阻和電容的匹配……………………254
7．1 Measuring Mismatch 失配的測(cè)量 ………………………………………………………254
7．2 Causes of Mismatch 失配的原因 ………………………………………………………257
7．2．1 Random Variation 隨機(jī)變化 ………………………………………………………………………257
7．2．2 Process Biases 工藝偏差 …………………………………………………………………………260
7．2．3 Interconnection Parasitics 互連寄生 ………………………………………………………………261
7．2．4 Pattern Shift 版圖移位 ……………………………………………………………………………263
7．2．5 Etch Rate Variations 刻蝕速率的變化 ……………………………………………………………265
7．2．6 Photolithographic Effects 光刻效應(yīng) ………………………………………………………………267
7．2．7 Diffusion Interactions 擴(kuò)散相互作用 ……………………………………………………………268
7．2．8 Hydrogenation 氫化 ………………………………………………………………………………270
7．2．9 Mechanical Stress and Package Shift 機(jī)械應(yīng)力和封裝漂移 ……………………………………271
7．2．10 Stress Gradients 應(yīng)力梯度 ………………………………………………………………………274
7．2．11 Temperature Gradients and Thermoelectrics 溫度梯度和熱電效應(yīng) ……………………………283
7．2．12 Electrostatic Interactions 靜電影響 ………………………………………………………………288
7．3 Rules for Device Matching 器件匹配規(guī)則 ……………………………………………295
7．3．1 Rules for Resistor Matching 電阻匹配規(guī)則 ………………………………………………………296
7．3．2 Rules for Capacitor Matching 電容匹配規(guī)則 ……………………………………………………300
7．4 Summary 小結(jié) …………………………………………………………………………303
7．5 Exercises 習(xí)題 …………………………………………………………………………304
Chapter 8 Bipolar Transistors 雙極型晶體管………………………………………………306
8．1 Topics in Bipolar Transistor Operation 雙極型晶體管的工作原理 ……………………306
8．1．1 Beta Rolloff β值下降 ……………………………………………………………………………308
8．1．2 Avalanche Breakdown 雪崩擊穿 …………………………………………………………………308
8．1．3 Thermal Runaway and Secondary Breakdown 熱擊穿和二次擊穿 ………………………………310
8．1．4 Saturation in NPN Transistors NPN晶體管的飽和狀態(tài) …………………………………………312
8．1．5 Saturation in Lateral PNP Transistors 寄生PNP管的飽和狀態(tài) …………………………………315
8．1．6 Parasitics of Bipolar Transistors 雙極型晶體管的寄生效應(yīng) ……………………………………318
8．2 Standard Bipolar Small-Signal Transistors 標(biāo)準(zhǔn)雙極型小信號(hào)晶體管 ………………320
8．2．1 The Standard Bipolar NPN Transistor 標(biāo)準(zhǔn)雙極型NPN晶體管 ………………………………320
8．2．2 The Standard Bipolar Substrate PNP Transistor 標(biāo)準(zhǔn)雙極工藝襯底PNP晶體管 ………………326
8．2．3 The Standard Bipolar Lateral PNP Transistor 標(biāo)準(zhǔn)雙極型橫向PNP晶體管 ……………………330
8．2．4 High-Voltage Bipolar Transistors 高電壓雙極型晶體管 …………………………………………337
8．2．5 Super-Beta NPN Transistors 超β NPN晶體管 …………………………………………………340
8．3 CMOS and BiCMOS Small-Signal Bipolar Transistors
CMOS和BiCMOS工藝小信號(hào)雙極型晶體管 …………………………………………341
8．3．1 CMOS PNP Transistors CMOS工藝PNP晶體管 ………………………………………………341
8．3．2 Shallow-Well Transistors 淺阱晶體管 ……………………………………………………………345
8．3．3 Analog BiCMOS Bipolar Transistors 模擬BiCMOS雙極型晶體管 ……………………………347
8．3．4 Fast Bipolar Transistors 高速雙極型晶體管 ……………………………………………………349
8．3．5 Polysilicon-Emitter Transistors 多晶硅發(fā)射極晶體管 ……………………………………………351
8．3．6 Oxide-Isolated Transistors 氧化隔離晶體管 ……………………………………………………354
8．3．7 Silicon-Germanium Transistors 鍺硅晶體管 ……………………………………………………356
8．4 Summary 小結(jié) …………………………………………………………………………358
8．5 Exercises 習(xí)題 …………………………………………………………………………358
Chapter 9 Applications of Bipolar Transistors 雙極型晶體管的應(yīng)用… …………………360
9．1 Power Bipolar Transistors 功率雙極型晶體管 …………………………………………361
9．1．1 Failure Mechanisms of NPN Power Transistors NPN功率晶體管的失效機(jī)制 …………………362
9．1．2 Layout of Power NPN Transistors 功率NPN晶體管的版圖 ……………………………………368
9．1．3 Power PNP Transistors PNP功率晶體管 …………………………………………………………376
9．1．4 Saturation Detection and Limiting 飽和檢測(cè)與限制 ……………………………………………378
9．2 Matching Bipolar Transistors 雙極型晶體管匹配 ………………………………………381
9．2．1 Random Variations 隨機(jī)變化 ……………………………………………………………………382
9．2．2 Emitter Degeneration 發(fā)射區(qū)簡(jiǎn)并 ………………………………………………………………384
9．2．3 NBL Shadow NBL陰影 …………………………………………………………………………386
9．2．4 Thermal Gradients 熱梯度 ………………………………………………………………………387
9．2．5 Stress Gradients 應(yīng)力梯度 ………………………………………………………………………391
9．2．6 Filler-Induced Stress 填充物誘生應(yīng)力 ……………………………………………………………393
9．2．7 Other Causes of Systematic Mismatch 系統(tǒng)失配的其他因素 ……………………………………395
9．3 Rules for Bipolar Transistor Matching 雙極型晶體管匹配設(shè)計(jì)規(guī)則 …………………396
9．3．1 Rules for Matching Vertical Transistors 縱向晶體管匹配規(guī)則 …………………………………397
9．3．2 Rules for Matching Lateral Transistors 橫向晶體管匹配規(guī)則 …………………………………400
9．4 Summary 小結(jié) …………………………………………………………………………402
9．5 Exercises 習(xí)題 …………………………………………………………………………403
Chapter 10 Diodes 二極管… ………………………………………………………………406
10．1 Diodes in Standard Bipolar 標(biāo)準(zhǔn)雙極工藝二極管 ……………………………………406
10．1．1 Diode-Connected Transistors 二極管連接形式的晶體管 ………………………………………406
10．1．2 Zener Diodes 齊納二極管 …………………………………………………………………………409
10．1．3 Schottky Diodes 肖特基二極管 …………………………………………………………………415
10．1．4 Power Diodes 功率二極管 ………………………………………………………………………420
10．2 Diodes in CMOS and BiCMOS Processes CMOS和BiCMOS工藝二極管 …………422
10．2．1 CMOS Junction Diodes CMOS結(jié)型二極管 ……………………………………………………422
10．2．2 CMOS and BiCMOS Schottky Diodes CMOS和BiCMOS肖特基二極管 ……………………423
10．3 Matching Diodes 匹配二極管 …………………………………………………………425
10．3．1 Matching PN Junction Diodes 匹配PN結(jié)二極管 ………………………………………………425
10．3．2 Matching Zener Diodes 匹配齊納二極管 ………………………………………………………426
10．3．3 Matching Schottky Diodes 匹配肖特基二極管 …………………………………………………428
10．4 Summary 小結(jié) …………………………………………………………………………428
10．5 Exercises 習(xí)題 …………………………………………………………………………429
Chapter 11 Field-Effect Transistors 場(chǎng)效應(yīng)晶體管… ……………………………………430
11．1 Topics in MOS Transistor Operation MOS晶體管的工作原理 ………………………431
11．1．1 Modeling the MOS Transistor MOS晶體管建模 …………………………………………………431
11．1．2 Parasitics of MOS Transistors 晶體管的寄生參數(shù) ………………………………………………438
11．2 Constructing CMOS Transistors 構(gòu)造CMOS晶體管 …………………………………446
11．2．1 Coding the MOS Transistor 繪制MOS晶體管版圖 ……………………………………………447
11．2．2 N-Well and P-Well Processes N阱和P阱工藝 …………………………………………………449
11．2．3 Channel Stop Implants 溝道終止注入 ……………………………………………………………452
11．2．4 Threshold Adjust Implants 閾值調(diào)整注入 ………………………………………………………453
11．2．5 Scaling the Transistor 按比例縮小晶體管 ………………………………………………………456
11．2．6 Variant Structures 不同的結(jié)構(gòu) ……………………………………………………………………459
11．2．7 Backgate Contacts 背柵接觸 ………………………………………………………………………464
11．3 Floating-Gate Transistors 浮柵晶體管 …………………………………………………467
11．3．1 Principles of Floating-Gate Transistor Operation 浮柵晶體管的工作原理 ………………………469
11．3．2 Single-Poly EEPROM Memory 單層多晶硅EEPROM存儲(chǔ)器 …………………………………472
11．4 The JFET Transistor JFET晶體管 ………………………………………………………474
11．4．1 Modeling the JFET JFET建模 ……………………………………………………………………474
11．4．2 JFET Layout JFET的版圖 ………………………………………………………………………476
11．5 Summary 小結(jié) …………………………………………………………………………479
11．6 Exercises 習(xí)題 …………………………………………………………………………479
Chapter 12 Applications of MOS Transistors MOS晶體管的應(yīng)用………………………482
12．1 Extended-Voltage Transistors 擴(kuò)展電壓晶體管 ………………………………………482
12．1．1 LDD and DDD Transistors LDD和DDD晶體管 ………………………………………………483
12．1．2 Extended-Drain Transistors 擴(kuò)展漏區(qū)晶體管 ……………………………………………………486
12．1．3 Multiple Gate Oxides 多層?xùn)叛趸?………………………………………………………………489
12．2 Power MOS Transistors 功率MOS晶體管 ……………………………………………491
12．2．1 MOS Safe Operating Area MOS安全工作區(qū) ……………………………………………………492
12．2．2 Conventional MOS Power Transistors 常規(guī)MOS功率晶體管 …………………………………498
12．2．3 DMOS Transistors DMOS晶體管 ………………………………………………………………505
12．3 MOS Transistor Matching MOS晶體管的匹配 ………………………………………511
12．3．1 Geometric Effects 幾何效應(yīng) ………………………………………………………………………513
12．3．2 Diffusion and Etch Effects 擴(kuò)散和刻蝕效應(yīng) ……………………………………………………516
12．3．3 Hydrogenation 氫化作用 ………………………………………………………………………520
12．3．4 Thermal and Stress Effects 熱效應(yīng)和應(yīng)力效應(yīng) …………………………………………………521
12．3．5 Common-Centroid Layout of MOS Transistors MOS晶體管的共質(zhì)心布局 …………………523
12．4 Rules for MOS Transistor Matching MOS晶體管的匹配規(guī)則 ………………………528
12．5 Summary 小結(jié) …………………………………………………………………………531
12．6 Exercises 習(xí)題 …………………………………………………………………………531
Chapter 13 Special Topics 一些專題… ……………………………………………………534
13．1 Merged Devices 合并器件 ………………………………………………………………534
13．1．1 Flawed Device Mergers 有缺陷的器件合并 ……………………………………………………535
13．1．2 Successful Device Mergers 成功的器件合并 ……………………………………………………539
13．1．3 Low-Risk Merged Devices 低風(fēng)險(xiǎn)合并 …………………………………………………………541
13．1．4 Medium-Risk Merged Devices 中度風(fēng)險(xiǎn)合并器件 ……………………………………………542
13．1．5 Devising New Merged Devices 設(shè)計(jì)新型合并器件 ……………………………………………544
13．1．6 The Role of Merged Devices in Analog BiCMOS 模擬BiCMOS中合并器件的作用 ………544
13．2 Guard Rings 保護(hù)環(huán) ……………………………………………………………………545
13．2．1 Standard Bipolar Electron Guard Rings 標(biāo)準(zhǔn)雙極電子保護(hù)環(huán) …………………………………546
13．2．2 Standard Bipolar Hole Guard Rings 標(biāo)準(zhǔn)雙極空穴保護(hù)環(huán) ……………………………………547
13．2．3 Guard Rings in CMOS and BiCMOS Designs CMOS和BiCMOS設(shè)計(jì)中的保護(hù)環(huán) …………548
13．3 Single-level Interconnection 單層互連 …………………………………………………551
13．3．1 Mock Layouts and Stick Diagrams 預(yù)布版和棒圖 ………………………………………………551
13．3．2 Techniques for Crossing Leads 交叉布線技術(shù) …………………………………………………553
13．3．3 Types of Tunnels 隧道的類型 ……………………………………………………………………555
13．4 Constructing the Padring 構(gòu)建焊盤環(huán) …………………………………………………557
13．4．1 Scribe Streets and Alignment Markers 劃片線與對(duì)準(zhǔn)標(biāo)記 ……………………………………557
13．4．2 Bondpads，Trimpads， and Testpads 焊盤、微調(diào)焊盤和測(cè)試焊盤 ………………………………558
13．5 ESD Structures ESD結(jié)構(gòu) ………………………………………………………………562
13．5．1 Zener Clamp 齊納鉗位 …………………………………………………………………………563
13．5．2 Two-Stage Zener Clamps 兩級(jí)齊納鉗位 ………………………………………………………565
13．5．3 Buffered Zener Clamp 緩沖齊納鉗位 …………………………………………………………566
13．5．4 VCES Clamp VCES鉗位 ……………………………………………………………………………568
13．5．5 VECS Clamp VECS鉗位 ……………………………………………………………………………569
13．5．6 Antiparallel Diode Clamps 反向并聯(lián)二極管鉗位 ………………………………………………570
13．5．7 Grounded-Gate NMOS Clamps 柵接地NMOS鉗位 …………………………………………570
13．5．8 CDM Clamps CDM鉗位 ………………………………………………………………………572
13．5．9 Lateral SCR Clamps 橫向SCR鉗位 ……………………………………………………………573
13．5．10 Selecting ESD Structures 選擇ESD結(jié)構(gòu) ………………………………………………………575
13．6 Exercises 習(xí)題 …………………………………………………………………………578
Chapter 14 Assembling the Die 組裝管芯… ………………………………………………581
14．1 Die Planning 規(guī)劃管芯 …………………………………………………………………581
14．1．1 Cell Area Estimation 單元面積估算 ………………………………………………………………582
14．1．2 Die Area Estimation 管芯面積估算 ………………………………………………………………584
14．1．3 Gross Profit Margin 總利潤(rùn)率 ……………………………………………………………………587
14．2 Floorplanning 布局 ………………………………………………………………………588
14．3 Top-Level Interconnection 頂層互連 ……………………………………………………594
14．3．1 Principles of Channel Routing 通道布線原理 ……………………………………………………594
14．3．2 Special Routing Techniques 特殊布線技術(shù) ………………………………………………………596
14．3．3 Electromigration 電遷徙 …………………………………………………………………………600
14．3．4 Minimizing Stress Effects 減小應(yīng)力效應(yīng) …………………………………………………………603
14．4 Conclusion 小結(jié) …………………………………………………………………………604
14．5 Exercises 習(xí)題 …………………………………………………………………………605
Appendix A Table of Acronyms Used in the Text 縮寫(xiě)詞匯表……………………………607
Appendix B The Miller Indices of a Cubic Crystal 立方晶體的米勒指數(shù)… ……………611
Appendix C Sample Layout Rules 版圖規(guī)則實(shí)例…………………………………………614
Appendix D Mathematical Derivations 數(shù)學(xué)公式推導(dǎo)… …………………………………622
Appendix E Sources for Layout Editor Software 版圖編輯軟件的出處… ………………627
Index 索引… ……………………………………………………………………………………628